A typical integrated circuit may include millions of devices or sub circuits, including numerous identical sub circuits. For example, a memory chip may contain millions of identical memory cells. Even if only one memory cell has defects, the entire chip may be rendered defective.
To increase yield, redundant memory cells are manufactured on the same chip. If some of the primary memory cells have defects, redundant memory cells can be used to replace the defective primary memory cells. This redundant configuration permits the semiconductor memory device to continue to operate in a normal state. The primary memory cells and redundant memory cells are all connected via fuses controlled by control circuits on the chip. As stated above, if a defective memory cell is discovered, a fuse coupled to the defective memory cell is blown and the redundant memory cell is connected instead. Accordingly, the semiconductor chip with defective primary memory cells can operate normally. This methodology is also used on other integrated circuits, particularly circuits having multiple identical units.
Highly integrated semiconductor memory devices have a fairly high manufacturing cost, which causes significant loss if any defective cells are discovered. This is why the memory devices include redundant memory cells for replacing defective primary memory cells. Types of fuses deployed in such semiconductor memory devices include electrical fuses selectively cut by the flow of excessive current, and laser fuses selectively blown by an applied laser beam. In contemporary systems, laser fuses are widely used due to their simplicity in use and layout. Electrical fuses are commonly used in semiconductor memory devices such as electrically erasable programmable read only memory (EEPROM) while laser fuses are often used in dynamic random access memory (DRAM).
Fuses are conventionally fabricated simultaneously with bond pads, which are used for bonding semiconductor chips in the packaging process. FIG. 1 illustrates a conventional laser fuse structure 14 formed in a laser fuse region and a bond pad 16 formed in a pad region. In a typical formation process, after a top metallization layer 10 is formed, a first passivation layer 12 is formed. Openings are formed in the bond pad regions through the passivation layer 12 to expose the underlying top metallization layer 10. In the laser fuse region, the passivation layer 12 is removed. An AlCu layer is then formed and patterned, forming a metal fuse link 14 and a bond pad 16. During the patterning of the AlCu layer, a thin anti-reflective coating (ARC) 15, which typically has a thickness of about 300 Å, is formed to reduce the reflection from the AlCu layer. The ARC 15 remains after the AlCu layer is patterned.
A second passivation layer 18 is formed covering the fuse link 14 and bond pad 16. In the bond pad region, a window 32 is opened in the second passivation layer 18 and the ARC 15, so that the bond pad 16 is exposed. In the fuse region, a window 30 is formed. Different from the bond pad region, a thin passivation layer 20, often referred to as remaining oxide, is left over the metal fuse link 14. The thin passivation layer 20 serves two purposes. It insulates the fuse link 14 from the external environment and protects the fuse link 14 from corrosion. In addition, if a laser repair is performed, the thin passivation layer 20 insulates the heat absorbed by metal fuse link 14 from escaping to achieve an effective burnout.
The conventional laser fuse formation processes suffer drawbacks, however. Since it is hard to accurately control the thickness of the remaining passivation layer 20 during the etching of the passivation layer 18, the subsequent laser burning process is adversely affected, and the laser repair yield is lowered. Additionally, two passivation layers 12 and 18 have to be formed, resulting in increased process complexity and cost. Accordingly, there is the need to improve the formation processes of laser fuses.